1. Field of the Invention
The present invention relates to semiconductor devices, in particular semiconductor integrated circuit devices using SALICIDE (SELF-ALIGHED SILICIDE) technology.
2. Discussion of Background
A LSIs have developed to larger-scale integration, SALISIDE technology has recently and widely been used to form a silicided layer on a silicon material in self-alignment in order to reduce contact resistance and to form an electrode such as a gate, a source and a drain which has a low resistivity.
An example wherein a process for producing a semiconductor device using the SALISIDE technology is applied to an NMOS transistor will be explained in reference to FIGS. 10-18.
First, a semiconductor substrate 1 (hereinbelow, referred to as the substrate 1) which is made from a P-type single-crystal silicon material has P-well regions 2 (hereinbelow, referred to as the P-wells 2) formed therein. After field insulating films 3 for isolation have been grown using a LOCOS process, a gate oxide film 4 is deposited on the entire face of the substrate. After that, a doped polysilicon film (or doped amorphous silicon film) 5a is deposited on the entire surface of the gate oxide film. After a photoresist film 6 is deposited on the entire surface of the doped polysilicon film, a photolithographic masking and etching technique is applied for patterning the resist film (see FIG. 10).
Next, the photoresist pattern 6 is used as a mask to etch the underlying doped polysilicon film 5a, thereby forming gate electrodes 5 which are used as conductive layers (see FIG. 11).
Next, after the photoresist film 6 is removed (see FIG. 12) impurities such as As and P are introduced from above the substrate 1 using an obligue rotational ion implantation process to form N.sup.- type LDD regions 7 (see FIG. 13).
Next, after a TEOS film 8 is deposited on the entire face of the substrate so as to have a film thickness of about 0.05-0.2 .mu.m (see FIG. 14), the TEOS film is etched by anisotropic dry etching to leave side spacers 9 on sidewalls of the gate electrodes 5 (see FIG. 15).
Next, in order to form N.sup.+ type source/drain regions 10 as conductive layers, impurities such as As and P are introduced from above the substrate 1 using an ion implantation process (see FIG. 16).
Now, a process for forming silicided layers on the gate electrodes 5 and on the source/drain regions 10 using the SALISIDE technology will be explained below.
Using e.g. a sputtering process, a Ti layer 11 as a metallic layer is deposited on the entire face of the substrate 1 which has the source/drain regions 10 formed as stated above (see FIG. 17).
After that, the substrate 1 is subjected to a heat treatment such as lamp annealing to modify the Ti layer 11 into TiSi.sub.2 layers 12 as silicided layers having a low resistivity by reaction of the Ti layer 11 with the underlying silicon material. Then, portions of the Ti layer 11 which have not reacted are removed using a solution such as H.sub.2 SO.sub.4 /H.sub.2 O.sub.2. In that manner, the TiSi.sub.2 layers 12 are formed only on the silicon material, i.e. on the gate electrodes 5 and on the source/drain regions 10 in self-alignment (see FIG. 18).
After that, the NMOS transistor is completed by forming interlayer insulating films and interconnect layers and heat treating (not shown).
By the way, LSIs are generally provided with an input output protection circuit to protect an internal circuit from electrostatic discharge failure (hereinbelow, referred to as ESD) etc. When the SALISIDE technology stated above is applied to form silicided layers having a low resistivity, such as the TiSi.sub.2 layer 12 on a gate 5 and source/drain regions of a transistor which constitutes the input output protection circuit, it becomes susceptible to be affected by a surge inputted from an external pad. In particular, corners 13 of the source/drain region 10 shown in FIG. 19 are susceptible to undergo electrical field convergence. The surge reaches the corners 13 through the resistor in the silicided layer (resistivity of the TiSi.sub.2 layer 12: about 13-18 .mu..OMEGA..cm), and junction breakdown is sucepticle to occur at the corners. The resistivity of the silicided layer is not more than one-tenth of the resistivity of the diffused layer in the source/drain region 10.
In order to cope with this problem, it has been proposed a production method which prevents such a silicided layer from being formed at a transistor constituting an input output protection circuit when LSIs are produced using the SALISIDE technology.
Such a method for producing semiconductor devices, which has been disclosed in e.g. U.S. Pat. No. 5,021,853, will be explained inreference to FIGS. 20(a)-20(c).
First, in accordance with steps similar to those shown in FIGS. 10-13, N.sup.- type LDD regions 7 are introduced after formation of gate electrodes 5. After a TEOS film has been deposited on the entire face of the substrate, selective etching is carried out by anaisotropic dry etching using a photoresist mask, thereby leaving the TEOS film 8a on a region with an NMOS transistor A region formed therein, and forming side pacers 9 on sidewalls of gate electrodes 5 on a region with an NMOS transistor B region formed therein (see FIG. 20(a)).
Next, in order to form N.sup.+ type source/drain regions 10, an ion implantation process is applied to implant impurities such as As and P from above the substrate 1 (see FIG. 20(b)).
Then, a Ti layer is deposited on the entire face of the substrate by e.g. a sputtering process, and a heat treatment such as lamp annealing is given to modify the Ti layer 11 on the silicon material into TiSi.sub.2 layers 12. After that, portions of the Ti layer which have not reacted is removed. And in this manner, no TiSi.sub.2 layer 12 is formed on the NMOS transistor A region with the TEOS film 8a formed thereon, and the TiSi.sub.2 layers 12 are selectively formed on the gate electrodes 5 and on the source/drain regions 10 on the NMOS transistor B region (see FIG. 20(c)).
As a result, when the silicided layers having a low resistivity are formed using the SALISIDE technology, a region where no silicided layer is formed is selectively produced on the common substrate 1.
According to the production method just above mentioned, when the ion implantation is made for forming the source/drain regions 10, the NMOS transistor A region receives the implantation from above the TEOS film 8a, and the NMOS transistor B region receives the implantation from above the silicon substrate 1 which the TEOS film 8 has been removed. As a result, the NMOS transistor A and the NMOS transistor B have different impurity distribution in their source/drain regions 10. Although it is possible to equalize the impurity distribution in the source/drain regions 10 by adding an extra ion implantation step, the fabrication processes become complicated.
A semiconductor device fabrication process by another proposal, which has been proposed to improved this problem, will be explained in reference to FIGS. 21(a)-21(e).
Firstly, in accordance with steps similar to those shown in FIG. 10-FIG. 16, N.sup.- type LDD regions 7 are formed after formation of gate electrodes 5. After a TEOS film is deposited on the entire face of the substrate, the entire face is subjected to etching to form side spacers 9. After that, N.sup.+ type source/drain regions 10 are formed.
Next, a second TEOS film 14 is deposited on the entire face of the substrate (see FIG. 21(a)). After a photoresist film 15 is formed on the entire face of the second TEOS film, a photolithographic technique is applied to pattern the photoresist film. Selective etching is carried out by anisotropic dry etching using the patterned photoresist film 15 as a mask, thereby leaving the second TEOS film 14a on the NMOS transistor A region, and to form second side spacers 16 on the gate electrodes 5 on the NMOS transistor B region. Since the gate electrodes 5 have already been formed with the first side spacers 9, the second side spacer 16 are formed on outer surfaces of the first side spacers 9 (see FIG. 21(b)).
After that, the photoresist film 15 is removed (see FIG. 21(c)), and a Ti layer 11 is deposited on the entire face of the substrate by e.g. a sputtering process (FIG. 21(d)). Then, a heat treatment, such as lamp annealing is performed given to react the Ti layer 11 on the silicon material to form TiSi.sub.2 layers 12. Portions of the Ti layer 11 which have not reacted are removed. In this manner, no TiSi.sub.2 layer 12 is formed on the NMOS transistor A region which the second TEOS film 14a formed thereon, and the TiSi.sub.2 layers 12 are selectively formed on the gate electrodes 5 and on the source/drain regions 10 on the NMOS transistor B region (FIG. 21(e)).
Although the problem of creation of different impurity distribution in the source/drain regions 10 can be solved by applying the SALICIDE technology using the second TEOS film 14a as a mask after formation of the source/drain regions 10, the second side spacers 16 are formed on the sidewalls of the gate electrodes 5 when the second TEOS film 14a is patterned. As a result, the area of the TiSi.sub.2 layers 12 on the source/drain regions decreases in the NMOS transistor B region by the second side spacers 16, and the diffused layer resistor under the second spacer 16 between paired source and drain works as a series resistor to deteriorate the operation speed of the element.
It is an object of the present invention to solve those problems, and to provide a highly reliable semiconductor device with a high operation speed, wherein a SALICIDE technology is applied to form a silicided layer with a low resistivity on a conductive layer made of a silicon material, wherein a high resistivity region without such a silicided layer is selectively provided to be free from different impurity distribution in source/drain regions between the region with the silicided layer formed therein and the high resistivity region, and wherein the operation speed of an element can be prevented from deteriorating in the silicided layer formation region due to an increase in resistor which is caused by a decrease in the area of the silicided layer.
The foregoing and other objects have been attained by providing a semiconductor device comprising a semiconductor substrate; a conductive layer on the substrate, which is made from a silicon material; and a silicided layer on the conductive layer, which is formed by salicide technology; wherein the silicided layer is partly constituted by a high resistivity silicided layer with N ions or O ions introduced therein.
The present invention also provides a method for preparing a semiconductor device, comprising the steps of forming on a semiconductor substrate a gate electrode to be a conductive layer, the substrate being made from a single-crystal silicon material, the gate electrode being made from a polysilicon material, and forming a side spacer on a sidewall of the gate electrode after formation of an LDD region by ion implantation, and then forming by ion implantation source/drain regions to be a conductive layer; implanting N ions or O ions into a predetermined region using a resist mask; depositing a metallic layer on the entire face of the substrate; and giving a heat treatment to the substrate to in self-alignment silicide portions of the metallic layer which are located on the gate electrode and on the source/drain regions, and then removing portions of the metallic layer which have not reacted.
It is preferable that after the formation of gate electrodes and the source/drain regions, the implantation of N ions or O ions into the predetermined region is made, and the metallic layer is deposited on the entire face of the substrate, and then the heat treatment causes the metallic layer to be silicided in self-alignment, thereby forming a high resistivity silicided layer on the gate electrode and on the source/drain regions in the N ion implanted region or O ion implanted region, and a low resistivity silicided layer on the gate electrode and on the source/drain regions in a region other than the N ion implanted region or O ion implanted region.
It is preferable that after the formation of gate electrodes and the source/drain regions, the metallic layer is deposited on the entire face of the substrate, and the implantation of N ions or O ions into the predetermined region is made, and then the heat treatment causes the metallic layer to be silicided in self-alignment, thereby forming a high resistivity silicided layer on the gate electrode and on the source/drain regions in the N ion implanted region or O ion implanted region, and a low resistivity silicided layer on the gate electrode and on the source/drain regions in a region other than the N ion implanted region or O ion implanted region.
It is preferable that after the formation of gate electrodes and the source/drain regions, the metallic layer is deposited on the entire face of the substrate, and the heat treatment causes the metallic layer to be silicided in self-alignment, and then the implantation of N ions or O ion into the predetermined region is made, thereby forming a high resistivity silicided layer on the gate electrode and on the source/drain regions in the N ion implanted region or O ion implanted region, and a low resistivity silicided layer on the gate electrode and on the source/drain regions in a region other than the N ion implanted region or O ion implanted region.
It is preferable that after the formation of gate electrodes and the source/drain regions, the gate electrodes and the source/drain regions have an epitaxial layer selectively grown thereon, and then the implantation of N ions or O ions and the deposition of the metallic layer are carried out.
It is preferable that the metallic layer is a Ti layer, the Ti layer is deposited on the entire face of the substrate, a protective film which resists H.sub.2 SO.sub.4 /H.sub.2 O.sub.2 is formed on the entire surface of the Ti layer, the implantation of N ions or O ions into the predetermined region is made using the resist mask, the resist mask is removed, and the remainder of the resist mask is removed using H.sub.2 SO.sub.4 /H.sub.2 O.sub.2, and then the protective film is removed.
The present invention also provides a method for preparing a semiconductor device, comprising the steps of forming on a semiconductor substrate gate electrodes, the substrate being made from a single-crystal silicon material, the gate electrodes being made from a polysilicon material, and forming a side spacer on a sidewall of the gate electrodes after formation of an LDD region by ion implantation, and then forming source/drain regions by ion implantation; selectively forming a metallic layer in a predetermined region on the substrate; and giving a heat treatment to the substrate to in self-alignment silicide the metallic later on the gate electrodes and on the source/drain regions, and then removing portions of the metallic layer which have not reacted; whereby a region with a low resistivity silicided layer formed therein and a region without a low resistivity silicided layer formed therein are provided on the gate electrodes and on the source/drain regions.
It is preferable that the metallic layer is a Ti layer, the Ti layer is deposited on the entire face of the substrate, a protective film which resists H.sub.2 SO.sub.4 /H.sub.2 O.sub.2 is formed on the entire surface of the Ti layer, the protective film is etched using a resist mask to be left in the predetermined region, after removal of the resist mask the remainder of the resist mask is removed using H.sub.2 SO.sub.4 /H.sub.2 O.sub.2, and the Ti layer which underlies the protective film is etched using the protective film as a mask, and then the protective film is removed, whereby the metallic layer is selectively formed in the predetermined region on the substrate.
It is preferable that the protective film is an Si.sub.3 N.sub.4 layer.
The present invention also provides a semiconductor device comprising a semiconductor substrate; a conductive layer on the substrate, which is made from a silicon material; and a silicided layer on the conductive layer, which is formed by salicide technology; wherein a high resistivity region is provided by forming on the conductive layer for connection with an external pad a high resistivity silicided layer with N ions or O ions introduced therein so as to surround in an annular manner a contact hole for connection with the external pad, or by forming on the conductive layer for connection with the external pad no silicided layer so as to surround in an annular manner the contact hole for connection the external pad.
The present invention also provides a semiconductor device comprising silicided layers formed on an input driver gate electrode and an output driver gate electrode, and on source/drain regions on a semiconductor substrate by salicide technology; the source/drain regions lying in an output driver, and being connected to an external pad and the input driver gate electrode; a contact hole A for connection with the external pad; and a contact hole B for connection with the input driver gate electrode; wherein the contact hole A is arranged at a side nearer to the output driver gate electrode than the contact hole B, and a high resistivity region is provided by forming a high resistivity silicided layer with N ions or O ions introduced therein at locations which occupy between and around the contact hole A and the contact hole B, or by forming no silicided layer at the locations.
The present invention also provides a semiconductor device comprising silicided layers formed on an input driver gate electrode and an output driver gate electrode, and on source/drain regions on a semiconductor substrate by salicide technology; an external pad; the source/drain regions lying in an output driver; and the external pad, the output driver source/drain regions, and the input driver gate electrode being connected by coupled interconnect layers; wherein a high resistivity region is provided by forming a high resistivity silicided layer with N ions or O ions introduced therein at locations which occupy around a contact hole in the interconnect layer on the output driver source/drain region and on the input driver gate electrode for connection with the interconnect layer, or by forming no silicided layer at the locations.
It is preferable that when the high resistivity silicided layer with N ions or O ions introduced therein is provided, no high resisitivity silicided layer is formed at a location near to a boundary portion between the source/drain regions and a field insulating film.
In a semiconductor device according to the present invention, the silicided layer which has been formed on the semiconductor substrate by salicide technology is partly constituted by the high resistivity silicided layer which has N ions or O ions introduced thereinto. This means that a low resistivity silicided layer region and the high resistivity silicided layer regions are both formed on conductive layers made from a silicon material on the semiconductor substrate. As a result, the high resistivity silicided layer can be formed on a portion of the conductive layer for e.g. an input output protection circuit, which is unsuitable for formation of a low-value resistor, depending to applications. The arrangement can improve degrees of freedom in circuitry design and obtain a highly reliable semiconductor device.
A method for producing a semiconductor device according to the present invention include the step to form the silicided layer by salicide technology after formation of the gate electrode and source/drain regions, and the step to implant N ions or O ions into the predetermined region using the resist mask. As a result, the N ion (or O ion) implanted region has the high resistivity silicided layer formed therein, and other regions have the low resistivity silicided layer formed therein, improving degrees of freedom in circuitry design and facilitating the fabrication of a highly reliable semiconductor device.
Such a method can prevent impurity distribution in the source/drain regions in the N ion (or O ion) implanted region and that in the other regions from being different, and avoid an increase in resistance due to a decrease in the area of the low resistivity silicided layer by formation of an extra side spacer, thereby obtaining a highly reliable semiconductor device with high operation speed.
According to an embodiment of the present invention, after formation of the gate electrodes and the source/drain regions, N ions or O ions are implanted into the predetermined region, and then the metallic layer is deposited to be silicided. As a result, metal atoms are prevented from arriving at a deep position near to a PN junction unlike a case wherein N ions (or O ions) are implanted after deposition of the metallic layer, and a deterioration in reliability such as junction leak is avoidable.
According to another embodiment of the present invention, after deposition of the metallic layer, N ions or O ions are implanted into the predetermined region, and then the metallic layer is silicided. Because the N ions (or O ions) are implanted from above the metallic layer, they are prevented from diffusing to a deep position in the semiconductor substrate to restrain a variation in resistance to hot carrier in the element.
According to another embodiment of the present invention, N ions or O ions are implanted into the predetermined region after the metallic layer which has been formed the entire face of the substrate is silicided in self-alignment. As a result, the number of the steps following the master step decreases to improve efficiency in production.
According to another embodiment of the present invention, the gate electrode and the source/drain regions have an epitaxial layer selectively grown thereon, and then implantation of N ions or O ions and deposition of a metallic layer are made. As a result, the silicided layer is formed at a higher position by the thickness of the epitaxial layer to allow the source/drain regions to be formed at a shallow position in the semiconductor substrate, thereby contributing a decrease in junction capacitance.
According to another embodiment of the present invention, the Ti layer is used as the metallic layer, the protective film which resists H.sub.2 SO.sub.4 /H.sub.2 O.sub.2 is formed on the Ti layer, and N ions or O ions are implanted using the resist mask. The reminders of the resist mask which has left after removal of the resist mask are removed using H.sub.2 SO.sub.4 /H.sub.2 O.sub.2. Although the Ti layer has properties to be attacked by H.sub.2 SO.sub.4 /H.sub.2 O.sub.2, the formation of the protective film on the Ti layer prevents the Ti layer from being exposed to H.sub.2 SO.sub.4 /H.sub.2 O.sub.2 at the time of removing the remaining portions of the resist mask, avoiding erosion of the Ti layer. As a result, the silicided layer which is made from Ti can be formed in a reliable manner even if H.sub.2 SO.sub.4 /H.sub.2 O.sub.2 is used for removal of the resist mask.
According to a semiconductor device fabrication process of the present invention, after formation of the gate electrode and the source/grain regions, the metallic layer is selectively formed on the predetermined region, and the metallic layer is silicided to form on the gate electrode and on the source/drain regions the region with the low resistivity silicided layer formed therein and the region without the low resistivity silicided layer. As a result, it is easy to provide the region without the low resistivity silicided layer formed therein on a gate electrode and on source/drain regions for e.g. an input output protection circuit, which is unsuitable for formation of a low-value resistor, depending to applications. This arrangement can improve degrees of freedom in circuitry design and facilitate fabrication of a highly reliable semiconductor device.
Such a method can prevent impurity distribution in the source/drain regions in the region with the low resistivity silicided layer formed therein and that in the region without the low resistivity silicided layer formed therein from being different unlike the prior art, and avoid an increase in electrical resistance due to a decrease in the area of the low resistivity silicided layer by formation of an extra side spacer, thereby obtaining a highly reliable semiconductor device with high operation speed.
According to another embodiment of the present invention, the Ti layer is used as the metallic layer, and the protective film which resists H.sub.2 SO.sub.4 /H.sub.2 O.sub.2 is formed on the Ti layer. The protective film is patterned using the resist mask. After removal of the resist mask, the remaining portions of the resist mask are removed using H.sub.2 SO.sub.4 /H.sub.2 O.sub.2. The Ti layer is etched using the left protective film as a mask to selectively form the Ti layer on the predetermined region. As a result, the Ti layer which is left for the subsequent step is covered by the protective film at the time of removing the resist mask, avoiding erosion of the Ti layer due to exposure to H.sub.2 SO.sub.4 /H.sub.2 O.sub.2. In this manner, the low resistivity silicided layer which is made from Ti can be formed in a reliable manner even if H.sub.2 SO.sub.4 /H.sub.2 O.sub.2 is used for removal of the resist mask.
According to another embodiment of the present invention, the Si.sub.3 N.sub.4 layer can be used as the protective film to reliably and easily realize the advantage offered by the protective film noted above.
In a semiconductor device according to the present invention, the high resistivity region is formed on the conductive layer for connection with an external pad by forming the high resistivity silicided layer with N ions or O ions introduced thereinto so as to surround a contact hole portion for connecting with the external pad or by forming no silicided layer. Such an arrangement can prevent a surge inputted from the external pad from reaching an internal circuit or a corner of source/drain regions (conductive layer) which are susceptible to junction breakdown, which can have an adverse effect on the device. In this manner, the junction breakdown due to the surge can be prevented to improve an input protective function against the surge.
According to another embodiment of the present invention, in the output driver, the contact hole A for connection with the external pad is located at a side nearer to the gate electrode than the contact hole B for connection with the gate electrode for the input driver on the common source/drain regions. The high resistivity region is formed by forming the high resistivity silicided layer with N ion or O ion introduced thereinto so as to occupy between and surround the contact hole A portion and the contact hole B portion or forming no silicided layer. Formation of the high rsistivity region can prevent the surge inputted through the external pad from reaching a corner or the source/drain region, and the gate electrode for the input driver, avoiding junction breakdown due to the surge, and improving an input protective function against the surge.
Since the contact hole A for connection with the external pad is arranged at a location nearer to the gate electrode than the contact hole B for connection with the input driver, a delay in output signal can be decreased.
According to another embodiment of the present invention, the external pad, the source/drain regions in the output driver, and the gate electrode in the input driver are sequentially connected by the coupled interconnect layers. As a result, the contact hole for connection with the external pad and the contact hole for connection with the gate electrode in the input driver get common on the source/drain regions in the output driver, allowing not only the area of the source/drain regions to decrease but also junction capacity to lower.
Since the high resistivity region is formed around the contact hole portion for connection with the external pad on the source/drain regions and on the gate electrode in the input driver for connecting with the interconnect layer, the surge inputted from the external pad can be prevented from reaching a corner in the source/drain regions or the input driver, avoiding junction breakdown and improving an input protective function.
According to another embodiment of the present invention, because the high resistivity silicided layer with N ions or O ions introduced thereinto is not formed in the vicinity of a boundary portion with the field insulting film on the source/drain regions, deterioration such as junction leak due to damage by implantation of N ions (or O ions) is prevented from occurring in the vicinity of the boundary portion where a thin oxide film is formed by bird's beak at the time of forming the field insulting film.